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David Patterson

Turing Award


The fast and energy-efficient microprocessors that power billions of smartphones, tablets and other electronic devices today have their roots in Professor David Patterson’s groundbreaking work on computer architectures in the 1980s.

At the time, most computer scientists believed that the best way to utilise semiconductors’ growing capabilities was to create more complex instruction sets for computer processors to carry out tasks. Professor Patterson took the opposite view, co-authoring a seminal 1980 paper that made the case for a reduced instruction set computer, or RISC.

With the RISC design, processors would execute simpler instructions but more of them, and at a faster pace. While this approach was controversial, it proved to be far more efficient than complex instruction sets, and more suitable for microprocessors, which were shrinking every year. By the 1990s, RISC-based processors were dominant, and they currently make up 99 percent of all microprocessors produced annually.

Beyond RISC, Professor Patterson and his colleagues also pioneered the Redundant Array of Independent Disks (RAID) storage approach, which uses an array of inexpensive disk drives to outperform single, large expensive ones. By configuring for redundancy, for example, the array’s reliability far exceeds that of the single large drive. 

For his trailblazing work, Professor Patterson was awarded the Turing Award in 2017 alongside another scientist, with the award committee lauding their “systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry”. 

He is also a fellow of the ACM, Institute of Electrical and Electronics Engineers, Computer History Museum, and other organisations, and was elected into the Silicon Valley Engineering Hall of Fame, American Academy of Arts and Sciences, National Academy of Engineering and National Academy of Sciences.

He has co-authored seven books, including the foundational textbook titled Computer Architecture: A Quantitative Approach, and is currently Pardee Professor of Computer Science and Professor Emeritus at the University of California, Berkeley, Distinguished Engineer at Google, where he is working on computer architectures for machine learning, and Vice-Chair of the Board of Directors of the RISC-V Foundation, which promotes innovation based on RISC-V, a free, RISC-based instruction set architecture.